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1/34 october 2005 m45pe10 1 mbit, low voltage, page-er asable serial flash memory with byte-alterability and a 33 mhz spi bus interface features summary 1mbit of page-erasable flash memory page write (up to 256 bytes) in 11ms (typical) page program (up to 256 bytes) in 1.2ms (typical) page erase (256 bytes) in 10ms (typical) sector erase (512 kbit) 2.7 to 3.6v single supply voltage spi bus compatible serial interface 33mhz clock rate (maximum) deep power-down mode 1 a (typical) electronic signature ? jedec standard two-byte signature (4011h) more than 100,000 write cycles more than 20 year data retention packages ? ecopack? (rohs compliant) figure 1. packages so8 (mn) 150 mil width 8 1 vdfpn8 (mp) (mlp8)
m45pe10 2/34 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 chip select (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 reset (reset ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 write protect (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 an easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 a fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 active power, standby power and deep power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . 7 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 read data bytes (read). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 page write (pw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 page erase (pe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 deep power-down (dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 release from deep power-down (rdp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/34 m45pe10 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
m45pe10 4/34 summary description the m45pe10 is a 1mbit (128k x 8 bit) serial paged flash memory accessed by a high speed spi-compatible bus. the memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. the page write instruction consists of an integrated page erase cycle fol- lowed by a page program cycle. the memory is organized as 2 sectors, each con- taining 256 pages. each page is 256 bytes wide. thus, the whole memory can be viewed as con- sisting of 512 pages, or 131,072 bytes. the memory can be erased a page at a time, using the page erase instruction, or a sector at a time, using the sector erase instruction. in order to meet environmental requirements, st offers these devices in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an st trademark. ecopack speci- fications are available at: www.st.com. figure 2. logic diagram figure 3. so and vdfpn connections note: 1. there is an exposed die paddle on the underside of the mlp8 package. this is pulled, internally, to v ss , and must not be allowed to be connected to any other voltage or signal line on the pcb. 2. see package mechanical section for package di- mensions, and how to identify pin-1. table 1. signal names reset ai07403 s v cc m45pe10 v ss w q c d c serial clock d serial data input q serial data output s chip select w write protect reset reset v cc supply voltage v ss ground 1 ai07404 2 3 4 8 7 6 5 w s v cc v ss c dq reset m45pe10
5/34 m45pe10 signal description serial data output (q). this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d). this input signal is used to transfer data serially into the device. it receives in- structions, addresses, and the data to be pro- grammed. values are latched on the rising edge of serial clock (c). serial clock (c). this input signal provides the timing of the serial interface. instructions, address- es, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q ) changes after the falling edge of serial clock (c). chip select (s ). when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal read, program, erase or write cycle is in progress, the device will be in the stan dby power mode (this is not the deep power-down mode). driving chip select (s ) low selects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. reset (reset ). the reset (reset ) input provides a hardware reset for the memory. in this mode, the outputs are high impedance. when reset (reset ) is driven high, the memory is in the normal operating mode. when reset (re- set ) is driven low, the me mory will enter the reset mode, provided that no internal operation is cur- rently in progress. driving reset (reset ) low while an internal operation is in progress has no effect on that internal operation (a write cycle, program cycle, or erase cycle). write protect (w ). this input signal puts the de- vice in the hardware pr otected mode, when write protect (w ) is connected to v ss , causing the first 256 pages of memory to become read-only by pro- tecting them from write, program and erase oper- ations. when write protect (w ) is connected to v cc , the first 256 pages of memory behave like the other pages of memory.
m45pe10 6/34 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the fa lling edge of serial clock (c). the difference between the two modes, as shown in figure 5. , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 4. bus master and memory devices on the spi bus note: the write protect (w ) signal should be driven, high or low as appropriate. figure 5. spi modes supported ai04043b bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w rp w rp w rp ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
7/34 m45pe10 operating features sharing the overhead of modifying data to write or program one (or more) data bytes, two instructions are required: write enable (wren), which is one byte, and a page write (pw) or page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal cy- cle (of duration t pw or t pp ). to share this overhead, the page write (pw) or page program (pp) instruction allows up to 256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, pro- vided that they lie in consecutive addresses on the same page of memory. an easy way to modify data the page write (pw) instruction provides a con- venient way of modifying data (up to 256 contigu- ous bytes at a time), and simply requires the start address, and the new data in the instruction se- quence. the page write (pw) instruction is entered by driving chip select (s ) low, and then transmitting the instruction byte, three address bytes (a23-a0) and at least one data byte, and then driving chip select (s ) high. while chip select (s ) is being held low, the data bytes are written to the data buffer, starting at the address given in the third ad- dress byte (a7-a0). when chip select (s ) is driven high, the write cycle starts. the remaining, un- changed, bytes of the data buffer are automatically loaded with the values of the corresponding bytes of the addressed memory page. the addressed memory page then automatically put into an erase cycle. finally, the addressed memory page is pro- grammed with the contents of the data buffer. all of this buffer management is handled internally, and is transparent to the user. the user is given the facility of being able to alter the contents of the memory on a byte-by-byte basis. for optimized timings, it is recommended to use the page write (pw) instru ction to write all con- secutive targeted bytes in a single sequence ver- sus using several page write (pw) sequences with each containing only a few bytes (see page write (pw) and ac characteristics (33mhz oper- ation) ). a fast way to modify data the page program (pp) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. this might be: ? when the designer is programming the device for the first time ? when the designer knows that the page has already been erased by an earlier page erase (pe) or sector erase (se) instruction. this is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available ? when the designer knows that the only changes involve resetting bits to 0 that are still set to 1. when this method is possible, it has the additional advantage of minimising the number of unnecessary erase operations, and the extra stress incurred by each page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted byte s in a single sequence versus using several page program (pp) se- quences with each containing only a few bytes (see page program (pp) and ac characteristics (33mhz operation) ). polling during a write, program or erase cycle a further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (t pw , t pp , t pe , or t se ). the write in progress (wip) bit is provided in the status register so that the application program can mon- itor its value, polling it to establish when the previ- ous cycle is complete. reset an internal power on reset circuit helps protect against inadvertent data writes. addition protec- tion is provided by driving reset (reset ) low dur- ing the power-on process, and only driving it high when v cc has reached the correct voltage level, v cc (min). active power, standby power and deep power-down modes when chip select (s ) is low, the device is select- ed, and in the active power mode. when chip select (s ) is high, the device is dese- lected, but could remain in the active power mode until all internal cycles have completed (program, erase, write). the device then goes in to the standby power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the deep power-down (dp) in- struction) is executed. the device consumption drops further to i cc2 . the device remains in this mode until another specif ic instruction (the re- lease from deep power-down and read electron- ic signature (res) instruction) is executed. all other instructions are ignored while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions.
m45pe10 8/34 status register the status register contains two status bits that can be read by the read status register (rdsr) instruction. wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write, program or erase cycle. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. table 2. status register format note: wel and wip are volatile read-only bits (wel is set and re- set by specific instructions; wip is automatically set and re- set by the internal logic of the device). protection modes the environments where non-volatile memory de- vices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the m45pe10 features the following data protection mechanisms: power on reset and an internal timer (t puw ) can provide protection against inadvertant changes while the power supply is outside the operating specification. program, erase and write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ? power-up ? reset (reset ) driven low ? write disable (wrdi) instruction completion ? page write (pw) in struction completion ? page program (pp) instruction completion ? page erase (pe) instruction completion ? sector erase (se) instruction completion the hardware protected mode is entered when write protect (w ) is driven low, causing the first 256 pages of memory to become read-only. when write protect (w ) is driven high, the first 256 pages of memory behave like the other pages of memory the reset (reset ) signal can be driven low to protect the contents of the memory during any critical time, not just during power-up and power-down. in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertant write, program and erase instructions while the device is not in active use. b7 b0 0 0 0 0 0 0 wel wip
9/34 m45pe10 memory organization the memory is organized as: 512 pages (256 bytes each). 131,072 bytes (8 bits each) 2 sectors (512 kbits, 65536 bytes each) each page can be individually: ? programmed (bits are programmed from 1 to 0) ? erased (bits are erased from 0 to 1) ? written (bits are changed to either 0 or 1) the device is page or sector erasable (bits are erased from 0 to 1). table 3. memory organization figure 6. block diagram sector address range 1 10000h 1ffffh 0 00000h 0ffffh ai07405 s w control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder c d q status register 00000h 1ffffh 000ffh reset 10000h first 256 pages can be made read-only
m45pe10 10/34 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) after chip select (s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in table 4. every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. in the case of a read data bytes (read), read data bytes at higher speed (fast_read) or read status register (rdsr) in struction, the shifted-in instruction sequence is fo llowed by a data-out se- quence. chip select (s ) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page write (pw), page program (pp), page erase (pe), se ctor erase (se), write enable (wren), write disable (wrdi), deep power-down (dp) or release from deep power- down (rdp) instruction, chip select (s ) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (s ) must driven high when the number of clock pulses after chip select (s ) being driven low is an exact multiple of eight. all attempts to access the memory array during a write cycle, program cycle or erase cycle are ig- nored, and the internal write cycle, program cycle or erase cycle continues unaffected. table 4. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdid read identification 1001 1111 9fh 0 0 1 to 3 rdsr read status register 0000 0101 05h 0 0 1 to read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to pw page write 0000 1010 0ah 3 0 1 to 256 pp page program 0000 0010 02h 3 0 1 to 256 pe page erase 1101 1011 dbh 3 0 0 se sector erase 1101 1000 d8h 3 0 0 dp deep power-down 1011 1001 b9h 0 0 0 rdp release from deep power-down 1010 1011 abh 0 0 0
11/34 m45pe10 write enable (wren) the write enable (wren) instruction ( figure 7. ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set pri- or to every page write (pw), page program (pp), page erase (pe), and sect or erase (se) instruc- tion. the write enable (wren) instruction is entered by driving chip select (s ) low, sending the in- struction code, and then driving chip select (s ) high. figure 7. write enable (wren) instruction sequence write disable (wrdi) the write disable (wrdi) instruction ( figure 8. ) resets the write enable latch (wel) bit. the write disable (wrdi) in struction is entered by driving chip select (s ) low, sending the instruc- tion code, and then driving chip select (s ) high. the write enable latch (wel) bit is reset under the following conditions: ?power-up ? write disable (wrdi) instruction completion ? page write (pw) instruction completion ? page program (pp) instruction completion ? page erase (pe) instruction completion ? sector erase (se) instruction completion figure 8. write disable (wrdi) instruction sequence c d ai02281e s q 2 1 34567 high impedance 0 instruction c d ai03750d s q 2 1 34567 high impedance 0 instruction
m45pe10 12/34 read identification (rdid) the read identification (r did) instruction allows the 8-bit manufacturer identification to be read, fol- lowed by two bytes of device identification. the manufacturer identification is assigned by jedec, and has the value 20h for stmicroelectronics. the device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (40h), and the memory capacity of the device in the second byte (11h). any read identification (rdid) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first select ed by driving chip select (s ) low. then, the 8-bit instruction code for the in- struction is shifted in. this is followed by the 24-bit device identification, stored in the memory, being shifted out on serial data output (q), each bit be- ing shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 9. the read identification (rdid) instruction is termi- nated by driving chip select (s ) high at any time during data output. when chip select (s ) is driven high, the device is put in the standby power mode. once in the standby power mode, the device waits to be se- lected, so that it can receive, decode and execute instructions. table 5. read identificati on (rdid) data-out sequence figure 9. read identification (rdid) in struction sequence and data-out sequence manufacturer identification device identification memory type memory capacity 20h 40h 11h c d s 2 1 3456789101112131415 instruction 0 ai06809 q manufacturer identification high impedance msb 15 1413 3210 device identification msb 16 16 18 28 29 30 31
13/34 m45pe10 read status register (rdsr) the read status register (rdsr) instruction al- lows the status register to be read. the status register may be read at any time, even while a program, erase or write cycle is in progress. when one of these cycles is in progress, it is rec- ommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register con- tinuously, as shown in figure 10. the status bits of the status register are as fol- lows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write, program or erase instruction is accepted. figure 10. read status register (rdsr) instruction sequence and data-out sequence c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
m45pe10 14/34 read data bytes (read) the device is first select ed by driving chip select (s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the mem- ory contents, at that address, is shifted out on se- rial data output (q), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 11. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shift- ed out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is termi- nated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data out- put. any read data by tes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 11. read data bytes (read) instruction sequence and data-out sequence note: address bits a23 to a17 are don?t care. c d ai03748d s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
15/34 m45pe10 read data bytes at higher speed (fast_read) the device is first select ed by driving chip select (s ) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 12. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shift- ed out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest ad- dress is reached, the address counter rolls over to 000000h, allowing the read sequence to be contin- ued indefinitely. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driv- en high at any time during data output. any read data bytes at higher speed (fast_read) in- struction, while an erase, program or write cycle is in progress, is rejected without having any ef- fects on the cycle that is in progress. figure 12. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence note: address bits a23 to a17 are don?t care. c d ai04006 s q 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24 bit address 0 c d s q 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35
m45pe10 16/34 page write (pw) the page write (pw) inst ruction allows bytes to be written in the memory. before it can be accept- ed, a write enable (wren) instruction must previ- ously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page write (pw) instruction is entered by driving chip select (s ) low, followed by the in- struction code, three address bytes and at least one data byte on serial data input (d). the rest of the page remains unchanged if no power failure occurs during this write cycle. the page write (pw) instruction performs a page erase cycle even if only one byte is updated. if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data exceeding the ad- dressed page boundary wrap round, and are writ- ten from the start address of the same page (the one whose 8 least significa nt address bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 13. . if more than 256 bytes are sent to the device, pre- viously latched data are discarded and the last 256 data bytes are guaranteed to be written correctly within the same page. if less than 256 data bytes are sent to device, they are correctly written at the requested addresses without having any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page write (pw) inst ruction to write all con- secutive targeted bytes in a single sequence ver- sus using several page write (pw) sequences with each containing only a few bytes (see ac characteristics (33mhz operation) ). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page write (pw) instruction is not executed. as soon as chip select (s ) is driven high, the self- timed page write cycle (whose duration is t pw ) is initiated. while the page wr ite cycle is in progress, the status register may be read to check the val- ue of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page write cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page write (pw) instruction applied to a page that is hardware protected is not executed. any page write (pw) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 13. page write (pw) instruction sequence note: 1. address bits a23 to a17 are don?t care 2. 1 n 256 c d ai04045 s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte n 765432 0 1 msb msb msb msb msb
17/34 m45pe10 page program (pp) the page program (pp) in struction allows bytes to be programmed in the memory (changing bits from 1 to 0, only). before it can be accepted, a write en- able (wren) instruction must previously have been executed. after the write enable (wren) in- struction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select (s ) low, followed by the in- struction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data exceeding the ad- dressed page boundary wrap round, and are pro- grammed from the start address of the same page (the one whose 8 least significant address bits (a7-a0) are all zero). chip select (s ) must be driv- en low for the entire duration of the sequence. the instruction sequence is shown in figure 14. . if more than 256 bytes are sent to the device, pre- viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor- rectly within the same page. if less than 256 data bytes are sent to device, they are correctly pro- grammed at the requested addresses without hav- ing any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted byte s in a single sequence versus using several page program (pp) se- quences with each containing only a few bytes (see ac characteristics (33mhz operation) ). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s ) is driven high, the self- timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page that is hardware protected is not executed. any page program (pp) instruction, while an erase, program or write cycle is in progress, is re- jected without having any effects on the cycle that is in progress. figure 14. page program (pp) instruction sequence note: 1. address bits a23 to a17 are don?t care 2. 1 n 256 c d ai04044 s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte n 765432 0 1 msb msb msb msb msb
m45pe10 18/34 page erase (pe) the page erase (pe) instruction sets to 1 (ffh) all bits inside the chosen page. before it can be ac- cepted, a write enable (wren) instruction must previously have been exec uted. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page erase (pe) instruction is entered by driving chip select (s ) low, followed by the in- struction code, and three address bytes on serial data input (d). any address inside the page is a valid address for the page erase (pe) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15. . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the page erase (pe) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page erase cycle (whose du- ration is t pe ) is initiated. while the page erase cy- cle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a page erase (pe) instruction applied to a page that is hardware protected is not executed. any page erase (pe) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 15. page erase (pe) instruction sequence note: address bits a23 to a17 are don?t care. 24 bit address c d ai04046 s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
19/34 m45pe10 sector erase (se) the sector erase (se) inst ruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decod- ed, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (s ) low, followed by the in- struction code, and three address bytes on serial data input (d). any address inside the sector (see table 3. ) is a valid address for the sector erase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 16. . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed sector erase cycle (whose du- ration is t se ) is initiated. while the sector erase cy- cle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a sector that contains a page that is hardware protected is not executed. any sector erase (se) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 16. sector erase (se) instruction sequence note: address bits a23 to a17 are don?t care. 24 bit address c d ai03751d s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
m45pe10 20/34 deep power-down (dp) executing the deep powe r-down (dp) instruction is the only way to put the device in the lowest con- sumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select (s ) high deselect s the device, and puts the device in the standby power mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, to reduce the standby current (from i cc1 to i cc2 , as specified in table 11. ). once the device has entered the deep power- down mode, all instructions are ignored except the release from deep powe r-down (rdp) instruc- tion. this releases the device from this mode. the deep power-down m ode automatically stops at power-down, and the device always powers-up in the standby power mode. the deep power-down (dp) instruction is entered by driving chip select (s ) low, followed by the in- struction code on serial data input (d). chip se- lect (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 17. . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep po wer-down (dp) instruc- tion is not executed. as soon as chip select (s ) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is re- jected without having any effects on the cycle that is in progress. figure 17. deep power-down (dp) instruction sequence c d ai03753d s 2 1 34567 0 t dp deep power-down mode stand-by mode instruction
21/34 m45pe10 release from deep power-down (rdp) once the device has entered the deep power- down mode, all instructions are ignored except the release from deep powe r-down (rdp) instruc- tion. executing this instruction takes the device out of the deep power-down mode. the release from deep power-down (rdp) in- struction is entered by driving chip select (s ) low, followed by the instruction code on serial data in- put (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 18. . the release from deep power-down (rdp) in- struction is terminated by driving chip select (s ) high. sending additional clock cycles on serial clock (c), while chip select (s ) is driven low, cause the instruction to be rejected, and not exe- cuted. after chip select (s ) has been driven high, fol- lowed by a delay, t rdp , the device is put in the standby power mode. chip select (s ) must re- main high at least until this period is over. the de- vice waits to be selected, so that it can receive, decode and execute instructions. any release from deep power-down (rdp) in- struction, while an erase, program or write cycle is in progress, is rejected without having any ef- fects on the cycle that is in progress. figure 18. release from deep power-down (rdp) instruction sequence c d ai06807 s 2 1 34567 0 t rdp stand-by mode deep power-down mode q high impedance instruction
m45pe10 22/34 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: ?v cc (min) at power-up, and then for a further delay of t vsl ?v ss at power-down usually a simple pull-up resistor on chip select (s ) can be used to ensure safe and proper power-up and power-down. to avoid data corruption and inadvertent write op- erations during power up, a power on reset (por) circuit is included. the logic inside the de- vice is held reset while v cc is less than the power on reset (por) threshold value, v wi ? all opera- tions are disabled, and the device does not re- spond to any instruction. moreover, the device ignores all write enable (wren), page write (pw) , page program (pp), page erase (pe) and sect or erase (se) instruc- tions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi thresh- old. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write, program or erase instructions should be sent until the later of: ?t puw after v cc passed the v wi threshold ?t vsl after wrap roundv cc passed the v cc (min) level these values are specified in table 6. . if the delay, t vsl , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instructions even if the t puw delay is not yet fully elapsed. as an extra protection, the reset (reset ) signal can be driven low for the whole duration of the power-up and power-down phases. at power-up, the device is in the following state: ? the device is in the standby power mode (not the deep power-down mode). ? the write enable latch (wel) bit is reset. normal precautions must be taken for supply rail decoupling, to stabilize the v cc supply. each de- vice in a system should have the v cc rail decou- pled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 0.1f). at power-down, when v cc drops from the operat- ing voltage, to below th e power on reset (por) threshold value, v wi , all operations are disabled and the device does not respond to any instruc- tion. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result.) figure 19. power-up timing v cc ai04009c v cc (min) v wi reset state of the device chip selection not allowed program, erase and write commands are rejected by the device tvsl tpuw time read access allowed device fully accessible v cc (max)
23/34 m45pe10 table 6. power-up timing and v wi threshold note: 1. these parameters are characterized only, over the temperature range ?40c to +85c. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). all usable status register bits are 0. maximum rating stressing the device outside the ratings listed in table 7. may cause permanent damage to the de- vice. these are stress ratings only, and operation of the device at these, or any other conditions out- side those indicated in the operating sections of this specification, is not implied. exposure to ab- solute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 7. absolute maximum ratings note: 1. compliant with jedec std j-std-020b (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t vsl 1 v cc (min) to s low 30 s t puw 1 time delay before the first write, program or erase instruction 1 10 ms v wi 1 write inhibit voltage 1.5 2.5 v symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see note 1 c v io input and output voltage (with respect to ground) ?0.6 4.0 v v cc supply voltage ?0.6 4.0 v v esd electrostatic discharge vo ltage (human body model) 2 ?2000 2000 v
m45pe10 24/34 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 8. operating conditions table 9. ac measurement conditions note: output hi-z is defined as the point where data out is no longer driven. figure 20. ac measurement i/o waveform table 10. capacitance note: sampled only, not 100% tested, at t a =25c and a frequency of 20 mhz. symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature ?40 85 c symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input and output timi ng reference voltages 0.3v cc to 0.7v cc v symbol parameter test condition min. max. unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (other pins) v in = 0v 6 pf ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
25/34 m45pe10 table 11. dc characteristics symbol parameter test condition (in addition to those in table 8. ) min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current (standby and reset modes) s = v cc , v in = v ss or v cc 50 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 10 a i cc3 operating current (fast_read) c = 0.1v cc / 0.9.v cc at 25mhz, q = open 6 ma c = 0.1v cc / 0.9.v cc at 33mhz, q = open 8 i cc4 operating current (pw) s = v cc 15 ma i cc5 operating current (se) s = v cc 15 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 av cc ?0.2 v
m45pe10 26/34 table 12. ac characteristics (25mhz operation) note: 1. t ch + t cl must be greater than or equal to 1/ f c (max) 2. value guaranteed by characterization, not 100% tested in production. 3. when using pp and pw instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) test conditions specified in table 8. and table 9. symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pw, pp, pe, se, dp, rdp, wren, wrdi, rdsr d.c. 25 mhz f r clock frequency for read instructions d.c. 20 mhz t ch 1 t clh clock high time 18 ns t cl 1 t cll clock low time 18 ns clock slew rate 2 (peak to peak) 0.03 v/ns t slch t css s active setup time (relative to c) 10 ns t chsl s not active hold time (relative to c) 10 ns t dvch t dsu data in setup time 5 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 10 ns t shch s not active setup time (relative to c) 10 ns t shsl t csh s deselect time 200 ns t shqz 2 t dis output disable time 15 ns t clqv t v clock low to output valid 15 ns t clqx t ho output hold time 0 ns t rlrh 2 t rst reset pulse width 10 s t rhsl t rec reset recovery time 3 s t shrh chip should have been deselected before reset is de-asserted 10 ns t whsl write protect setup time 50 ns t shwl write protect hold time 100 ns t dp 2 s to deep power-down 3 s t rdp 2 s high to standby power mode 30 s t pw (3) page write cycle time (256 bytes) 11 25 ms page write cycle time (n bytes) 10.2+ n*0.8/256 t pp (3) page program cycle time (256 bytes) 1.2 5ms page program cycle time (n bytes) 0.4+ n*0.8/256 t pe page erase cycle time 10 20 ms t se sector erase cycle time 1 5 s
27/34 m45pe10 table 13. ac characteristics (33mhz operation) note: 1. t ch + t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. 3. when using pp and pw instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) 4. details of how to find the date of marking are given in application note, an1995. 33mhz only available for products marked since week 40 of 2005 (4) test conditions specified in table 8. and table 9. symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pw, pp, pe, se, dp, rdp, wren, wrdi, rdsr d.c. 33 mhz f r clock frequency for read instructions d.c. 20 mhz t ch (1) t clh clock high time 13 ns t cl (1) t cll clock low time 13 ns clock slew rate 2 (peak to peak) 0.03 v/ns t slch t css s active setup time (relative to c) 10 ns t chsl s not active hold time (relative to c) 10 ns t dvch t dsu data in setup time 3 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 200 ns t shqz (2) t dis output disable time 12 ns t clqv t v clock low to output valid 12 ns t clqx t ho output hold time 0 ns t thsl top sector lock setup time 50 ns t shtl top sector lock hold time 100 ns t dp (2) s to deep power-down 3 s t rdp (2) s high to standby power mode 30 s t pw (3) page write cycle time (256 bytes) 11 25 ms page write cycle time (n bytes) 10.2+ n*0.8/256 t pp (3) page program cycle time (256 bytes) 1.2 5ms page program cycle time (n bytes) 0.4+ n*0.8/256 t pe page erase cycle time 10 20 ms t se sector erase cycle time 1 5 s
m45pe10 28/34 figure 21. serial input timing figure 22. write protect setup and hold timing c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c d s q high impedance w twhsl tshwl ai07439
29/34 m45pe10 figure 23. output timing figure 24. reset ac waveforms c q ai01449d s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv ai06808 reset trlrh s trhsl tshrh
m45pe10 30/34 package mechanical figure 25. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline note: drawing is not to scale. table 14. so8 narrow ? 8 lead plastic small outlin e, 150 mils body width, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e1.27??0.050?? h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 0 8 0 8 n8 8 cp 0.10 0.004 so-a e n cp b e a d c l a1 1 h h x 45?
31/34 m45pe10 figure 26. mlp8, 8-lead very thin dual flat package no lead, 6x5mm, package outline note: drawing is not to scale. table 15. mlp8, 8-lead very thin dual flat package no lead, 6x5mm, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 0.85 1.00 0.0335 0.0394 a1 0.00 0.05 0.0000 0.0020 a2 0.65 0.0256 a3 0.20 0.0079 b 0.40 0.35 0.48 0.0157 0.0138 0.0189 d 6.00 0.2362 d1 5.75 0.2264 d2 3.40 3.20 3.60 0.1339 0.1260 0.1417 e 5.00 0.1969 e1 4.75 0.1870 e2 4.00 3.80 4.20 0.1575 0.1496 0.1654 e 1.27 0.0500 l 0.60 0.50 0.75 0.0236 0.0197 0.0295 12 12 d e vdfpn-01 a2 a a3 a1 e1 d1 e e2 d2 l b
m45pe10 32/34 part numbering table 16. ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. example: m45pe10 ? v mp 6 t g device type m45pe = serial flash memory for data storage device function 10 = 1mbit (128k x 8) operating voltage v = v cc = 2.7 to 3.6v package mn = so8 (150 mil width) mp = vdfpn8 6x5mm (mlp8) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p or g = ecopack? (rohs compliant)
33/34 m45pe10 revision history table 17. document revision history date version description of revision 29-apr-2003 1.0 document written 04-jun-2003 1.1 description corrected of enteri ng hardware protected mode (w must be driven, and cannot be left unconnected). 04-dec-2003 1.2 v io (min) extended to ?0.6v, t pw (typ) and t pp (typ) improved. table of contents, warning about exposed paddle on mlp8, and pb-free options added. change of naming for vdfpn8 package. 25-jun-2004 1.3 soldering temperature information clarified for rohs compliant devices. device grade clarified. 22-sep-2004 2.0 document promoted to pr eliminary data. minor wording changes 08-oct-2004 3.0 document promoted to mature datasheet. no other changes 4-oct-2005 4.0 added ac characteristic s (33mhz operation) . an easy way to modify data , a fast way to modify data , page write (pw) and page program (pp) sections updated to explain optimal use of page write and page program instructions. updated i cc3 values in table 11., dc characteristics . updated table 16., ordering information scheme . added ecopack? information.
m45pe10 34/34 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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